1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor substrate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of metal-oxide-semiconductor (xe2x80x9cMOSxe2x80x9d) transistors, a gate conductor may be arranged upon a gate dielectric, which may be formed upon a substrate. Typically, the gate dielectric is laterally interposed between source and drain regions formed in the substrate, where the source and drain regions may be doped to opposite conductivity type (either n-type or p-type) than the substrate. N-type source/drain regions may be used to form n-channel transistors, and p-type source/drain regions may be used to form p-channel transistors. However, in complementary MOS (xe2x80x9cCMOSxe2x80x9d) circuits, both n-channel and p-channel transistors are employed within the same substrate. Consequently, xe2x80x9cwellsxe2x80x9d may be formed by selectively doping the region of the substrate underlying the subsequently formed gate conductors, thereby allowing a substrate of either conductivity type to be used. The wells are doped with an opposite conductivity type than that of the source and drain regions. In this manner, n-channel transistors may be formed in p-type wells, while p-channel transistors may be formed in n-type wells.
In some embodiments, a single n-type doped polysilicon gate material is used for the formation of the gate conductors of the NMOS and PMOS transistors. Due to the work function of the n-type polysilicon, a p-type threshold adjust implant is required for the formation of the PMOS transistor. As such, a surface channel NMOS transistor and a buried channel PMOS transistor is produced. Unfortunately, the buried channel PMOS transistor has poor short channel characteristics and, as a result, must be designed with a larger threshold voltage than the surface channel NMOS transistor to limit subthreshold leakage current. However, high threshold voltages may have a significant effect on performance of the circuit, particularly at low supply voltages.
An alternative approach to the single poly method is the formation of gate structures having opposite conductivity type. Such a method may be referred to as the xe2x80x9cdual polyxe2x80x9d or xe2x80x9cdual gatexe2x80x9d approach and includes an n-type doped polysilicon gate for the NMOS transistor and a p-type doped polysilicon gate for the PMOS transistor. Such a method produces a surface channel NMOS transistor and a surface channel PMOS transistor, thereby allowing the threshold voltage of the PMOS transistor to be approximately the same value as the NMOS transistor. Unfortunately, such a process is very costly to integrate into the fabrication of CMOS circuits due to the high number of masks which may be required to implant the wells and gate conductors. For instance, at least four patterned masking layers are typically needed for the doping of wells, channel dopant regions, and gates of a dual gate CMOS circuit using the xe2x80x9cdual polyxe2x80x9d method. Two masking layers are for the formation of wells and/or channel dopant regions of opposite conductivity type within the substrate and an additional two masking layers are for the formation of gate structures of opposite conductivity type overlying the wells. The high number of masks undesirably increases the processing costs and time of fabricating the circuit.
In some embodiments, source/drain regions may be doped simultaneously with the gate structures. However, in some cases, the gate structures of a CMOS circuit may be doped with impurities before the formation of the source/drain regions, thereby requiring additional masking layers. For example, the formation of a dual gate transistor pair in a memory circuit may require additional masking layers since source/drain regions may not be formed in conjunction with the doping of the gate structures. In such a circuit formation, gate structures may include an insulating cap above the gate electrode for subsequent formation of self-aligned contact schemes. In such an instance, an insulating layer may be formed upon a silicon layer prior to the patterning of the gate structures. As such, the silicon layer must be doped prior to the formation of the insulating layer. Masking steps are therefore needed in this case to form oppositely-doped gates in a dual poly approach, since the gates cannot be doped along with the subsequently formed source/drain regions.
Accordingly, it would be advantageous to develop a method for forming a CMOS integrated circuit, in which the NMOS transistor and PMOS transistor may have comparable threshold voltages. In particular, it would advantageous to form such an integrated circuit using fewer masking layers.
The problems outlined above may be in large part addressed by a method for processing a semiconductor substrate. In particular, a method is provided for forming first and second wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first and second portions of opposite conductivity type. The formation of the silicon layer may include the use of the single patterned layer or an additional patterned layer. The method as described herein may form a dual gate transistor pair, which includes a first well doped with well impurities of both conductivity types. More specifically, the first well may include a greater concentration of a well impurity of one conductivity type than a concentration of a well impurity of the other conductivity type. The dual gate transistor pair may include a second well doped with the well impurity of the lower concentration. A first gate structure doped with both conductivity types may be arranged upon one of the first and second wells, where the first gate structure has a greater concentration of gate impurities of one conductivity type than a concentration of the other conductivity type. In addition, a second gate structure doped with the gate impurity of the lower concentration may be arranged upon the other of the wells.
As stated above, the method includes forming first and second wells of opposite conductivity type using a single patterned layer. Such a method may include forming the single patterned layer over a portion of the semiconductor substrate and subsequently introducing first well dopants into the patterned layer and into exposed portions of the semiconductor substrate. The single patterned layer may then be removed so that second well dopants of opposite conductivity type may be introduced into the semiconductor substrate without the single patterned layer. Introducing the first and second well dopants may include forming respective first and second well dopant concentrations, where the first well dopant concentration may be higher than the second well dopant concentration. In a further embodiment, introducing first and second well dopants may include implanting such that a dose of the first well dopants is larger than a dose of the second well dopants. For example, the dose of the first well dopants may be up to approximately 5.0 times larger than the dose of second well dopants. More specifically, the dose of the first well dopants may be approximately 1.5 times to approximately 3.0 times larger than the dose of the second well dopants.
The method may further include forming a silicon layer having first and second portions of opposite conductivity type above the semiconductor substrate. In an embodiment, each of the first and second portions of the silicon layer may be arranged above one of the first and second wells. In addition, each of the portions may have an opposite conductivity type to the respective underlying well. Furthermore, the silicon layer may be patterned to form a gate structure above each of the first and second wells. In some embodiments, the silicon layer may be formed using an additional single patterned layer. For example, a silicon layer, which includes dopants of one conductivity type, may be deposited over the semiconductor substrate. An additional single patterned layer may be formed over a region of the silicon layer and gate dopants may be subsequently introduced into the additional single patterned layer and exposed portions of the silicon layer. Preferably, the gate dopants in such an embodiment are of opposite conductivity type to the conductivity type of the deposited silicon layer. In an alternative embodiment, the silicon layer may be formed by first depositing an undoped silicon layer over the semiconductor substrate. An additional single patterned layer may be formed over a region of the silicon layer and first gate dopants may be introduced into the additional single patterned layer and exposed portions of the silicon layer. The additional single patterned layer may then be removed so that second gate dopants may be introduced into the silicon layer without the additional single patterned layer. Preferably, the second gate dopants are of opposite conductivity type to the first gate dopants. Similar to the formation of the first and second well concentrations within the semiconductor substrate, introducing first and second gate dopants may form respective first and second gate dopant concentrations within the silicon layer. In one embodiment, the first gate dopant concentration may be higher than the second gate dopant concentration.
The method as described herein may further include introducing channel dopants into the semiconductor substrate. For example, first channel dopants may be introduced into the exposed portion of the semiconductor substrate prior to removing the single patterned layer arranged above the substrate. In one embodiment, the first channel dopants may be of the same conductivity type as the first well dopants. After removing the single patterned layer, second channel dopants may be introduced into the semiconductor substrate without the single patterned layer. Alternatively, second channel dopants may be introduced into the semiconductor substrate after forming the additional single patterned layer over a region of the silicon layer. In either embodiment, the second channel dopants may be of opposite conductivity type to the first channel dopants. Introducing first and second channel dopants may form respective first and second channel dopant concentrations. In such an embodiment, the first channel dopant concentration may be higher than the second channel dopant concentration.
In an embodiment, the method as described herein may be used to form an integrated circuit. In particular, the method may include using a single patterned layer to form wells of opposite conductivity type within a semiconductor substrate and a silicon layer having first and second portions of opposite conductivity type over the semiconductor substrate. The formation of the wells may include introducing first well dopants into the semiconductor substrate without the single patterned layer. A silicon layer may then be deposited above the semiconductor substrate followed by the formation of the single patterned layer over a region of the silicon layer. Second well dopants may then be introduced into the semiconductor substrate through exposed regions of the silicon layer to form a well having the same net conductivity type as the second well dopants. In a preferred embodiment, the second well dopants are of opposite conductivity type to the first well dopants. Forming the silicon layer may include introducing first gate dopants into exposed portions of the silicon layer and the single patterned layer and subsequently removing the single patterned layer. Second gate dopants may then be introduced into the silicon layer without the single patterned layer. As with the well dopants, the second gate dopants may be of opposite conductivity type to the first gate dopants. In addition, the method may include introducing first channel dopants into the semiconductor substrate without the patterned layer. In a preferred embodiment, the first channel dopants may be of the same conductivity type as the first well dopants. Alternatively or in addition, second channel dopants may be introduced into the semiconductor substrate after forming the single patterned layer. In one embodiment, the second channel dopants may be of opposite conductivity type to the first channel dopants. Introducing first and second channel dopants may form respective first and second channel dopant concentrations, where the first channel dopant concentration may be lower than the second channel dopant concentration.
The method as described herein may form a dual gate CMOS transistor, which includes a first well doped with well impurities of both conductivity types. The first well preferably includes a greater concentration of a well impurity of one conductivity type than a concentration of a well impurity of the other conductivity type. The transistor may also include a second well doped with the well impurity having the lower concentration. A first gate structure doped with gate impurities of both conductivity types may be arranged upon one of the first and second wells. The first gate structure may include a greater concentration of a gate impurity of one conductivity type than a concentration of a gate impurity of the other conductivity type. In an embodiment, the first well may have a net conductivity type opposite to that of the gate structure arranged over it. In addition, a second gate structure doped with the gate impurity having the lower concentration may be arranged upon the other of the first and second wells so that each well has a gate structure arranged upon it.